|Name of the course||Online||Lecture||Exercises||Lab|
The course 'Microprocessor Architecture' is an online course. Students attend from lecture halls or from home. Local presence is not required.
The course introduces design techniques in microprocessor architectures. The content is closely related to the book "Computer Architecture, 6th Edition" by Hennessy and Patterson. The theoretic part of the course is divided into modules that, depending on the course format, include lectures or virtual round-table discussions on each module. The practical part of the course is a combination of analytical exercises to train the theoretic content and some program compilation and execution examples on a free RISC-V microprocessor pipeline simulator. Participants require a basic knowledge on Linux (preferably Ubuntu) and a laptop or desktop computer to install the relevant software.
Having completed the course, students should know the basic types of system architectures and the principles of operation of microprocessor cores, understand microprocessor design techniques and how optimizations on instruction level, data level and thread level parallelism as well as the cache and memory subsystem affects core, chip and system performance.
The course "Microprocessor Architecture" can be completed stand-alone or in combination with the courses "SystemVerilog for Design" or "SystemVerilog for Verification". The course does not introduce basics in digital or analog engineering. Participants are recommended to have a at least a solid knowledge in digital engineering before applying for this course.
|1||Introduction to Computer Architecture - Von Neumann Architecture, Harvard Architecture, Classification by Flynn, Performance Equations, Amdahl's Law, Benchmarking, Semiconductor Technology, Moore's Law, Dennard Scaling, Instruction Set Architecture||[PDF*]|
|2||Introduction to Storage 1 - Physical and Logical Organization, Size and Speed, Address Spaces, Virtual and Physical Addresses, Address Translation Process, Translation Lookaside Buffer||[PDF*]|
|3||Introduction to Storage 2 - Cache Memory, Cache Hierarchy, Cache Coherency, Cache Performance, Cache Coherency Protocol, Memory Architectures (NUMA, COMA)||[PDF*]|
|4||Introduction to Processor Microarchitecture - Processor Pipeline, The Compilation and Linking Process, Data Dependencies,
Example-1: Cross-Compiling a "Hello World"-Program,
Example-2: Simulating a program on a Microprocessor Pipeline Simulator
|5||Instruction Level Parallelism 1 - Branch, Branch Delay Slot, Forwarding and Bypassing, Branch Scheduling and Bypassing, Superscalar Pipeline, Hardware Prediction and Speculation||[PDF*]|
|6||Instruction Level Parallelism 2 - Multiple Instruction Issue, Out of Order Execution, Register Renaming, Reorder Buffer, Reservation Station, Scoreboard, Tomasulu Algorithm, Very Long Instruction Word (VLIW)||[PDF*]|
|7||Data Level Parallelism - Overview (Vector, SIMD and GPU Architecture), Vector Register, SIMD Extensions, Massively Parallel GPU Architectures||[PDF*]|
|8||Thread Level Parallelism 1 - Introduction to Threads, Centralized Shared-Memory Multicore Acrhitecture, Directory-Based Cache Coherency Protocols, Snooping Cache Coherency Protocols,
Example-1: The MESI/MOESI Cache Coherence Protocol,
Example-2: Single-Chip Multicore with Distributed Cache Architecture (NUCA/NUMA)
|9||Thread Level Parallelism 2 - Distributed-Memory Multicore Architecture, Distributed Shared-Memory Multicore Architecture with Directory-Based Cache Coherence, Synchronization of Threads, (Spin) Locks, Models of Memory Consistency||[PDF*]|
Literature Computer Architecture, Hennessy and Patterson, 6th Edition
Morgan Kaufmann 2019, ISBN 978-0-12-811905-1