Introduction to Microprocessor Architecture

Name of the course	Online	Lecture	Exercises	Lab
Introduction to Microprocessor Architecture	✓	✓	✓	✗

Context

Preliminary courses:

• Introduction to Electrical Engineering [w3]
• Introduction to Digital Engineering [w3]

Recommended Preliminary courses:

• ASIC Design Tools Lab [w3]

Follow-on courses:

• Introduction to Digital Circuit Design [w3]
• SystemVerilog for Design [w3]
• SystemVerilog for Verification [w3]

Details

The course introduces design and implementation techniques of microprocessor architectures. Having completed the course, participants know the basic classifications of microprocessor architectures and principles of operation. The course is offered in a virtual classroom. Students attend from lecture halls or from home on their individual preference.

Course Records

Part	Content	BSc	MSc	File
	Student Guidance			[PDF]
1	Microprocessor Architecture: Advancements in Computer Designs, Moores Law, Dennard Scaling, Microarchitecture Concepts, von Neumann Architecture, Harvard Architecture, Classification by Flynn, Instruction Set Architecture, Computational Performance, Amdahl's Law, Benchmarking	✓	✓	[PDF]
2	Memory Management: Introduction to Memory Management, Volatile and Non-volatile Memory, Memory Hierarchies, Latency and Bandwidth, Organization of Memory, Address Translation, Physical and Virtual Addressing, Paging and Segmentation, Page Status and Control, Address Translation, Caches, Translation Lookaside Buffer, Introduction to Caches, Cache Organization, Cache Hierarchies, Cache Performance, Virtually Indexed Physically Tagged L1-Cache		✓	[PDF]
3	Pipelined Microarchitectures: Instruction Execution, Instruction Types and Formats, The Register File, The Concept of Pipeling, The Register File, Implementation of a Simple Pipeline, Pipeline Hazards, Pipeline Stalls and Interlocks, Pipeline Bypassing and Forwarding, Branch Penalties, Branch Delay Slot, Reducing Branch Penalties, Implementation of a Pipeline with Data Forwarding, Difficulties in Pipeline Implementation	✓	✓	[PDF]
4	Instruction Level Parallelism 1: Pipeline with Data Forwarding, Branch Delay Slot, Concepts of Instruction Level Parallelism, Data Dependence, Name Dependence, Data Hazard, Control Dependence, Exception Behaviour	✓	✓	[PDF]
5	Instruction Level Parallelism 2: Example on Tomasulo's Algorithm, Hardware Speculation with Reorder Buffer, Exception Handling with Reorder Buffer, Exceptions of Mispredicted Instructions, Hardware Speculation and Hazards, Multiple Instruction Issue, Very Long Instruction Word Architecture (VLIW), VLIW and Vector Architecture, Introduction to Multi-Threading, Multithreading vs. Multiprocessor, Threads and Shared Memory, Superscalar Execution, Levels of Scheduling		✓	[PDF]
6	Data Level Parallelism 1: Introduction to Vector Architectures, Features of the RISC-V Vector Architecture Extension (RV64V), Example on Dynamic Register Typing, Execution Time and Performance, Parallel Execution of Vector Elements, Multiply-Add Vector Architecture, Maximum Length and Vector Length Register, Strip Mining, Handling if-Statements, Multidimensional Arrays, Programming Vector Architectures	✓	✓	[PDF]
7	Data Level Parallelism 2: SIMD Extensions, SIMD Examples, Programming SIMD Architectures, Introduction to Graphics Processing Units (GPUs), GPU Microarchitecure Characteristics, Data Transfer in GPUs, Conditional Branching in GPUs, GPU Memory Architectures, GPU vs. Vector Architecture Comparison		✓	[PDF]
8	Thread Level Parallelism 1: Centralized Shared-Memory Multicore Architectures, Snooping Cache Coherency Protocols, Multicore Processor Performance Considerations	✓	✓	[PDF]
9	Thread Level Parallelism 2: Distributed Shared Memory Multicore Architectures, Directory-Based Cache Coherence, Hardware Primitives for Synchronizations, Spin Locks, Models of Memory Consistency		✓	[PDF]

Literature

[1] Computer Architecture, Hennessy and Patterson, 6th Edition
      Morgan Kaufmann 2019, ISBN 978-0-12-811905-1
[2] The RISC-V Reader, Patterson and Waterman, 1st Edition
      Strawberry Canyon LCC 2017, ISBN 978-0-9992491-1-6