Introduction to Microprocessor Architecture

Name of the course	Online	Lecture	Exercises	Lab
Intriduction to Microprocessor Architecture	✓	✓	✗	✓

The course 'Microprocessor Architecture' is an online course. Students attend from lecture halls or from home. Local presence is not mandatory.

The course introduces basic and advanced design techniques in microprocessor architectures. The content is closely related to the book "Computer Architecture, 6th Edition" by Hennessy and Patterson. The theoretic part of the course is divided into modules that, depending on the course format, include lectures or virtual round-table discussions. The practical part of the course is a combination of analytical exercises to train the theoretic content and some program compilation and execution examples. All practical examples are based on a the RISC-V architecture. Participants work on a free RISC-V online simulator to understand major design challenges of microprocessors. A basic knowledge on Linux is recommended and a laptop or desktop computer is needed if the course should be completed from home office.

Having completed the course, participants should know the basic structure of a microprocessor and the principles of operation. Participants should understand the basic techniques of microprocessor optimization at instruction level, data level and thread level, how cache designs and memory hierarchies affects microprocessor performance.

The course "Microprocessor Architecture" can be completed stand-alone or in combination with the courses SystemVerilog for Design [w3] or SystemVerilog for Verification [w3] or the ASIC-Tools Lab [w3]. The course does not introduce the basics in digital or analog engineering. Participants are recommended to have some knowledge in Digital Engineering [w3] before applying for this course.

Course content

Part	Content	Script*
1	Introduction - Von Neumann Architecture, Harvard Architecture, Classification by Flynn, Performance Equations, Amdahl's Law, Benchmarking, Semiconductor Technology, Moore's Law, Dennard Scaling, Instruction Set Architecture, Overview on Advancements in Design and Technology	[PDF]
2	Memory Management - Types of Memory, Memory Hierarchies, Latency and Bandwidth, Physical and Virtual Addressing, Address Translation, Caches, Cache Hierarchies, Cache Performance	[PDF]
3	Instruction Execution - Instruction Types, Instruction Formats, Register File, Pipeline, Pipeline Stages, Pipeline Hazards, Stalls and Interlocks, Bypassing and Forwarding, Branch Penalties, Branch Delay Slow, Reducing Branch Penalties, Difficulties in Pipeline Implementation	[PDF]
4	Instruction Level Parallelism - Concepts and Challenges, Basic Compiler Techniques, Advanced Branch Prediction, Dynamic Scheduling, Multiple Instruction Issue, Out-Of-Order Execution, Register Renaming, Scoreboard, Speculation, Tomasulo's Algorithm	[PDF]
5	Data Level Parallelism - Overview (Vector, SIMD and GPU Architecture), Vector Register, SIMD Extensions, Massively Parallel GPU Architectures	[PDF*]
6	Thread Level Parallelism 1 - Introduction to Threads, Centralized Shared-Memory Multicore Acrhitecture, Directory-Based Cache Coherency Protocols, Snooping Cache Coherency Protocols	[PDF*]
7	Thread Level Parallelism 2 - Distributed-Memory Multicore Architecture, Distributed Shared-Memory Multicore Architecture with Directory-Based Cache Coherence, Synchronization of Threads, (Spin) Locks, Models of Memory Consistency	[PDF*]

*under work

Literature

[1] Computer Architecture, Hennessy and Patterson, 6th Edition
      Morgan Kaufmann 2019, ISBN 978-0-12-811905-1