Introduction to the Digital ASIC Design Flow

Name of the course	Online	Lecture	Exercises	Lab
Digital ASIC Design Flow Lab	✓	✗	✗	✓

The 'Digital ASIC Design Flow Lab' offers a low-level entry into the world of digital ASIC design. It provides a set of practical laboratories for prospective engineering managers or future ASIC design engineers. The course introduces the major design steps in digital ASIC design projects. Lab exercises focus on the design flow from HDL-entry to synthesis and timing. Floorplanning and physical layout are not in primary focus but elements of the practical exercises. Important development procedures and project milestones are explained and their correlations to the digital engineering fundamentals are shown in practical exercises.

The course aims for engineering managers to define work packages, create time plans, interpret tools outputs and track development cycles. Candidates with a sound background in digital engineering are introduced to the complexity of a digital ASIC design development process and are trained on a contemporary up-to-date design environment as utilized in the industry.

There are no preliminaries to enroll for this course but to really benefit from attendance it is recommended to have some basic knowledge in Digital Engineering and Electrical Engineering as well as some practical experience with the Unix operating system. Knowledge in semiconductor technology is an advantage when it comes to physical layout and integration.

The lab is a barrier-free online course offered in a virtual classroom. Students need to be present during lab appointments to complete the course successfully. Physical presence at the campus is possible but not mandatory.

The course is completely based on the Cadence Design Environment using the Cadence Acacdemic License. This guarantees excellent tools documentation and support as well as regular tools updates so that the course offers an up-to-date design environment at industrial standards at all times.

Participants work on a ready-to-run digital ASIC design environment, on ready-to-run design flows and on ready-to-use designs during the entire course. It is not necessary to develop designs or to setup and configure design flows or tools. It is out of the scope of THIS course to introduce how a design is developed and how individual tools can be configured to address design characteristics.

The course offers eight lab exercises to get introduced to the general design flow as well as to specific design aspects and how they affect the design flow, e.g. Engineering Change Orders, low power, 3D-integration. The output of a sample exercise can be found here.

Please watch before registration!

This course is focused on ASICs.
What is an ASIC, FPGA, SOC? [w3]

This course is focused on the digital ASIC design flow.
What is the digital ASIC Design Flow? [w3]

Lab Exercises

Num	Description
1	Introduction to the Digital Design Flow
2	Introduction to the Digital ECO Flow
3	Static Timing Analysis of a Dual-Tone Multi-Frequency Reveiver (DMTF)
4	Synthesis of a Dual-Tone Multi-Frequency Reveiver (DMTF)
5	Power Profiling of a 10-bit CPU design at RTL level
6	Low-power implementation of a SiFive P670 RISC-V CPU core
7	3D Integration of a two-die RISC-V design
8	RTL to GDSII implementation of a tiny Digital Signal Processor (DSP)

Participants work on the labs remotely on a universities server using individual VNC sessions. Attendance from a computer room at the university is possible but a personal device is recommended to work from every place and outside the opening hours.

Literature

[1] CMOS VLSI Design, 4th edition by Weste Neil Harris David, 2010, ISBN-13 978-0321547743
[2] Application Specific Integrated Circuits, Michael Smith, 1997, ISBN-13 978-0201500226, [w3] or [w3]
[3] Cadence documentation and training material