ASIC Design Tools Lab

Name of the course Online Lecture Exercises Lab
ASIC Design Tools Lab ✗  ✗ 

The 'ASIC Design Tools Lab' is a course for prospective engineering managers or an orientation for prospective ASIC design engineers. The course covers the entire ASIC design process but puts a focus on the tools used in the front-end design process. This includes HDL design and verification, HDL synthesis, static timing analysis. Some important procedures and milestones of ASIC design projects are covered, i.e. design convergence and closure, verification convergence and closure, timing takedown and closure, power profiling, formal equivalence as well as engineering change orders.

To benefit from attendance it is recommended to have a solid basic knowledge in Digital Engineering and Electrical Engineering as well as some experience with shell script. A background in semiconductor technology is an advantage but not a must.

The 'ASIC Design Tools Lab' is a guided online course and as such offered completely in a virtual classroom. Students have to be present during lab appointments and deliver performance in the labs. Grades are awarded without explicit examination; if at all required as per regulations of the branch of study.

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The labs focus on managing the tools used for simulation, synthesis and static timing analysis. The course utilizes the Cadence Design Environment.

Having completed the course successfully, participants should understand the basic design flow for ASIC designs. They should be able to operate the front-end design flow, assess a reasonable use of tools and interpret outputs. Along the entire course participants operate on an existing design environment and on existing HDL designs. It is not in the objective of the course to create own or modify existing designs.

The scope of this course is the introduction of the ASIC design environment and the tools flow of the ASIC design process to qualify prospective engineering managers in defining reasonable work packages, time plans, design teams, milestones etc. for ASIC design projects. It is out of the scope of the course to educate R&D ASIC design engineers.

More details on the training exercises can be found here.

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Lab Experiments

Num Description
1 Introduction to the ASIC Design Flow
2 RTL Design Compiler (RC)
3 Static Timing Analysis (STA)
4 Global Timing Debug (GTD)
5 Logic Equivalence Check (LEC)
6 RTL Power Profiling
7 Basic Floorplanning
8 Engineering Change Order (ECO)


Cadence Education and Training material.