ASIC Design Tools Lab

Name of the course Online Lecture Exercises Lab
ASIC Design Tools Lab ✗  ✗ 

The 'ASIC Design Lab' is a course for engineering managers or a foundational course for future ASIC design engineers. The course has a focus on the tools used in the front-end design process, i.e. HDL simulation, synthesis and timing analysis. It is recommended to have a basic knowledge in Digital Engineering and Electrical Engineering as well as some experience with shell script. Knowledge in semiconductor technology is an advantage but not needed. The 'ASIC Design Lab' is a guided online course and as such offered in a virtual classroom.

10bit CPU

The labs focus on managing the tools used for simulation, synthesis and static timing analysis. The course utilizes the Cadence Design Environment.

Having completed the course successfully, students should understand the basic ASIC design flow. They should be able to operate the front-end design flow. This includes simulating existing HDL designs, synthesis and static timing analysis of existing designs as well as to manage ECOs.

It is clearly in the scope of this course to train engineering managers on managing engineering activities but absolutely out of the scope of the course to educate ASIC design engineers on implementation and optimization activities.

10bit CPU

Lab Experiments

Num Description
1 RTL Design Compiler (RC)
2 Static Timing Analysis (STA)
3 Global Timing Debug (GTD)
4 Logic Equivalence Check (LEC)
5 RTL Power Profiling
6 ASIC Full Flow