SystemVerilog for Design

Name of the course	Online	Lecture	Exercises	Lab
SystemVerilog for Design	✓	✓	✓	✓

The course 'SystemVerilog for Design' is a training on the design flow for Application Specific Integrated Circuits (ASICs) with SystemVerilog. The course has a focus on the front-end design from HDL entry to synthesis and static timing analysis. It is recommended to have a solid knowledge in Digital Engineering and Electrical Engineering as well as basic experience in shellscript and programming. Knowledge in CMOS technology is an advantage but not a must. 'SystemVerilog for Design' is an online course and as such offered in a virtual classroom.

'SystemVerilog for Design' is organized in two parts. The first part is a lecture on the Hardware Description Language (HDL) SystemVerilog with a focus on digital hardware design at Register-Transfer-Level (RTL). Students write SystemVerilog code for small design examples, then simulate the design, perform a synthesis and a static timing analysis. All testbenches are at designer level and secure only basic functionality. Inspections of the netlists and timing reports show how the tools synthesize digital hardware from HDL code. Part Two is a series of lab exercises on the digital ASIC design flow for larger designs. Part 2 introduces some relevant standard procedures as they are part of the daily work of a design engineer. The exercises focus on tools used for synthesis, static timing analysis and if time permits on power profiling, logic equivalence check and the ECO flow. Part 2 utilizes the Cadence Design Environment. The exercises are Rapid Adoption Kits (RAKs) as applied for trainings in industry.

Having completed the course successfully, students will understand the ASIC design flow and will be able to work with the front-end design flow, implement RTL designs, run synthesis and static timing analysis and optimize the results. The back-end design flow and verification techniques for digital designs are out of the scope of the course. There is a separate course SystemVerilog for Verification on the verification of complex digital designs.

More details on the exercises can be found here.

Course Records

No.	Content	Doc
1	Introduction to SystemVerilog	[PDF]
2	Modeling at Register-Transfer-Level	[PDF]
3	Net and variable types	[PDF]
4	Organizing designs with packages	[PDF]
5.1	SystemVerilog at Register-Transfer-Level (1 of 2)	[PDF]
5.2	SystemVerilog at Register-Transfer-Level (2 of 2)	[PDF]
6	Synthesis at Register-Transfer-Level	[PDF]
7	Modeling sequential logic and memory	[PDF]
8	Intentional and unintentional inferred latches	[PDF]

Laboratory

Name	Content	Doc
FLOW RAK	ASIC design flow example	[PDF*]
GENUS RAK	RTL Synthesis Compiler	[PDF*]
Tempus GTD RAK	Global Timing Debug	[PDF*]
RTL-VCD RAK	Power Profiling	[PDF*]
LEC RAK	Logic Equivalence Check	[PDF*]
ECO RAK	Engineering Change Orders (RTL to GDSII)	[PDF*]

*Cadence Design Systems Confidentiality Notice

Literature

[1] RTL Modeling with SystemVerilog for Simulation and Synthesis, Stuart Sutherland,
      published by Sutherland HDL, Oregon 2017, ISBN 078-1-5467-7634-5
[2] CMOS VLSI Design, Weste & Harris, Addison Wesley Publ., ISBN 0-321-54774-8