SystemVerilog for Design
| Name of the course | Online | Lecture | Exercises | Lab |
|---|---|---|---|---|
| SystemVerilog for Design | ✓ | ✓ | ✓ | ✗ |
The course 'SystemVerilog for Design' introduces the front-end design flow for Application Specific Integrated Circuits (ASICs) with SystemVerilog. The course has a focus on HDL entry, synthesis and static timing analysis. It is recommended to complete the ASIC Design Lab in advance and have a solid knowledge in Digital Engineering and Electrical Engineering as well as basic experience in shell script and programming in general. Base knowledge in CMOS technology is an advantage but not a must. 'SystemVerilog for Design' is an online course and as such offered in a virtual classroom.
'SystemVerilog for Design' introduces the Hardware Description Language (HDL) SystemVerilog with a focus on digital hardware design at Register-Transfer-Level (RTL). Students write SystemVerilog code for small design examples, simulate the design to secure its basic functionality, perform a synthesis and a static timing analysis. Inspections of the netlists and timing reports show how the tools synthesize digital hardware from HDL code.
Having completed the course, students should be able to implement simple RTL designs, synthesize a netlist, perform a static timing analysis and interpret the results.
The back-end design flow and verification techniques for digital designs are out of the scope of the course. There is a separate course SystemVerilog for Verification on the verification of complex digital designs.
Records
| No. | Content | Doc |
|---|---|---|
| 1 | Introduction to SystemVerilog | [PDF] |
| 2 | Modeling at Register-Transfer-Level | [PDF] |
| 3 | Net and variable types | [PDF] |
| 4 | Organizing designs with packages | [PDF] |
| 5.1 | SystemVerilog at Register-Transfer-Level (1 of 2) | [PDF] |
| 5.2 | SystemVerilog at Register-Transfer-Level (2 of 2) | [PDF] |
| 6 | Synthesis at Register-Transfer-Level | [PDF] |
| 7 | Modeling sequential logic and memory | [PDF] |
| 8 | Intentional and unintentional inferred latches | [PDF] |
Exercises
| Num | Description | Link |
|---|---|---|
| 1 | History. RTL and gate-level modeling. ASIC vs. FPGA. Simulation. Synthesis. Logic equivalence. Examples: Simple design and testbench implementation. Device under test. | [.tgz] |
| 2 | Modules and procedural blocks. Coding style. Task and function. Compiler directives. Modules. Examples: Simple Decoder and Adder. |
[.tgz] |
| 3 | States and values. Literals. Date and Net Types. Ports. Constants. Constants. Patameters. Examples: Parametrized RAM and Adder example. |
[.tgz] |
| 4 | Types. Packages. Explicit, conditional, wildcard imports. Arrays, Structs, Unions, Enums. Examples: CPU and GPU package and Arithmetic Logic Unit examples. |
[.tgz] |
| 5 | Concatenate, Conditional, Bitwise and Comparison operator. Examples: Barrel Shifter, Signed and Unsigned Adder. |
[.tgz] |
| 6 | If-Else statement. Loop Statements. Always Statement. Continue and break statements. Examples: Set-Reset Flip-Flop, MUX, BCD-Encoder. |
[.tgz] |
| 7 | Always comb statement. Continuous assignment. Functions and procedures. Examples: ALU dataflow, SRAM, Algorithmic Multiplier. |
[.tgz] |
| 8 | Blocking and Non-blocking statement. Asynchronous signals. Finite State Machines. Examples: FSMs, RAMs, Johnson Counter, Flip-Flops and Simple SPI. |
[.tgz] |
| 9 | FSM implementations. Intended and unindended latches. Priority decoders. Examples: FSM with unique case, x default and x assign, state sequencer, reverse one-hot. |
[.tgz] |
Literature
[1] RTL Modeling with SystemVerilog for Simulation and Synthesis, Stuart Sutherland,published by Sutherland HDL, Oregon 2017, ISBN 078-1-5467-7634-5
[2] CMOS VLSI Design, Weste & Harris, Addison Wesley Publ., ISBN 0-321-54774-8