Coverage Summary Report, Instance-Based
Top Level SummaryLegend and Help
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Instance name: tb_top.fma_top_I.classifier_result_single_I Type name: classifier_result File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/classifier_result.sv |
Coverage Summary Report, Instance-Based
| Overall | Overall Covered | Block | Expression | Toggle | FSM State | FSM Transition | Assertion | CoverGroup | CoverGroup Covered | name |
|---|---|---|---|---|---|---|---|---|---|---|
| 93.34% | 93.33% (98/105) | 92.45% (49/53) | n/a | 94.23% (49/52) | n/a | n/a | n/a | n/a | n/a | classifier_result_single_I |
Uncovered Block Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.classifier_result_single_I Type name: classifier_result File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/classifier_result.sv Number of uncovered blocks: 4 of 53 Number of unreachable blocks: 0 |
Count Block Line Kind Origin Source Code
------------------------------------------------------------------------------
0 12 99 true part of 99 if (|{abs_zero_a, abs_zero_b}) begin
0 24 147 a case item of 124 begin
0 25 153 a case item of 124 begin
0 34 204 a case item of 180 begin
Uncovered Expression Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.classifier_result_single_I Type name: classifier_result File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/classifier_result.sv Number of uncovered expressions: 0 of 0 Number of unreachable expressions: 0 |
index | grade | line | expression ------------------------------------------------------------------------------------- 0 items found
Uncovered Toggle Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.classifier_result_single_I Type name: classifier_result File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/classifier_result.sv Number of uncovered signal bits: 3 of 52 Number of unreachable signal bits: 0 Number of signal bits partially toggled(rise): 0 of 52 Number of signal bits partially toggled(fall): 0 of 52 |
Hit(Full) Hit(Rise) Hit(Fall) Signal ----------------------------------------------------------- 0 0 0 pos_inf_b 0 0 0 neg_inf_b 0 0 0 abs_inf_b
Uncovered Fsm Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.classifier_result_single_I Type name: classifier_result File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/classifier_result.sv |
0 items found
Uncovered Assertion Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.classifier_result_single_I Type name: classifier_result File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/classifier_result.sv Number of uncovered assertions: 0 of 0 |
Finished Failed Assertion Line Source Code ------------------------------------------------------------------------------------ 0 items found
Uncovered CoverGroup Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.classifier_result_single_I Type name: classifier_result File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/classifier_result.sv Number of uncovered cover bins: 0 of 0 |
0 items found