Coverage Summary Report, Instance-Based
Top Level SummaryLegend and Help
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Instance name: tb_top.fma_top_I.normalization_shift_I Type name: normalization_shift File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/normalization_shift.sv |
Coverage Summary Report, Instance-Based
| Overall | Overall Covered | Block | Expression | Toggle | FSM State | FSM Transition | Assertion | CoverGroup | CoverGroup Covered | name |
|---|---|---|---|---|---|---|---|---|---|---|
| 90.60% | 95.90% (678/707) | 90.00% (9/10) | 85.71% (6/7) | 96.09% (663/690) | n/a | n/a | n/a | n/a | n/a | normalization_shift_I |
Uncovered Block Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.normalization_shift_I Type name: normalization_shift File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/normalization_shift.sv Number of uncovered blocks: 1 of 10 Number of unreachable blocks: 0 |
Count Block Line Kind Origin Source Code ------------------------------------------------------------------------------ 0 10 150 a case item of 106 begin
Uncovered Expression Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.normalization_shift_I Type name: normalization_shift File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/normalization_shift.sv Number of uncovered expressions: 1 of 7 Number of unreachable expressions: 0 |
index | grade | line | expression ------------------------------------------------------------------------------------- 2.1 | 75.00% (3/4) | 120 | ((! addend_correction_left) && addend_correction_right) && (! (addend_res_exponent <= e_min)) index: 2.1 grade: 75.00% (3/4) line: 120 source: else if (!addend_correction_left&&addend_correction_right&&!(addend_res_exponent<=e_min))// check that exp not subnorm ((! addend_correction_left) && addend_correction_right) && (! (addend_res_exponent <= e_min))
<---------1----------> <----------2----------> <-------------3--------------> index | hit | rval | <1> <2> <3> --------------------------------------- 2.1.4 | 0 | 0 | 1 - -
Uncovered Toggle Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.normalization_shift_I Type name: normalization_shift File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/normalization_shift.sv Number of uncovered signal bits: 27 of 690 Number of unreachable signal bits: 0 Number of signal bits partially toggled(rise): 0 of 690 Number of signal bits partially toggled(fall): 0 of 690 |
Hit(Full) Hit(Rise) Hit(Fall) Signal ----------------------------------------------------------- 0 0 0 mantissa_raw[163] 0 0 0 res_uncut[0] 0 0 0 res_uncut_corrected[0] 0 0 0 d_upper_bound[6] 0 0 0 d_upper_bound[5] 0 0 0 d_upper_bound[4] 0 0 0 d_upper_bound[3] 0 0 0 d_upper_bound[2] 0 0 0 d_upper_bound[1] 0 0 0 d_upper_bound[0] 0 0 0 d_lower_bound[7] 0 0 0 d_lower_bound[6] 0 0 0 d_lower_bound[5] 0 0 0 d_lower_bound[4] 0 0 0 d_lower_bound[3] 0 0 0 d_lower_bound[2] 0 0 0 d_lower_bound[1] 0 0 0 d_lower_bound[0] 0 0 0 e_min[11] 0 0 0 e_min[10] 0 0 0 e_min[6] 0 0 0 e_min[5] 0 0 0 e_min[4] 0 0 0 e_min[3] 0 0 0 e_min[2] 0 0 0 e_min[1] 0 0 0 e_min[0]
Uncovered Fsm Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.normalization_shift_I Type name: normalization_shift File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/normalization_shift.sv |
0 items found
Uncovered Assertion Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.normalization_shift_I Type name: normalization_shift File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/normalization_shift.sv Number of uncovered assertions: 0 of 0 |
Finished Failed Assertion Line Source Code ------------------------------------------------------------------------------------ 0 items found
Uncovered CoverGroup Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.normalization_shift_I Type name: normalization_shift File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/normalization_shift.sv Number of uncovered cover bins: 0 of 0 |
0 items found