Coverage Summary Report, Instance-Based
Top Level SummaryLegend and Help
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Instance name: tb_top.fma_top_I.leading_zero_anticipator_I.leading_zero_counter_I Type name: leading_zero_counter File name: /home/mfertig/riscv2/riscv_FPU/external/riscv_bb/leading_zero_counter/leading_zero_counter.sv |
Coverage Summary Report, Instance-Based
| Overall | Overall Covered | Block | Expression | Toggle | FSM State | FSM Transition | Assertion | CoverGroup | CoverGroup Covered | name |
|---|---|---|---|---|---|---|---|---|---|---|
| 92.99% | 86.04% (228/265) | 100.00% (1/1) | n/a | 85.98% (227/264) | n/a | n/a | n/a | n/a | n/a | leading_zero_counter_I |
Uncovered Block Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.leading_zero_anticipator_I.leading_zero_counter_I Type name: leading_zero_counter File name: /home/mfertig/riscv2/riscv_FPU/external/riscv_bb/leading_zero_counter/leading_zero_counter.sv Number of uncovered blocks: 0 of 1 Number of unreachable blocks: 0 |
Count Block Line Kind Origin Source Code ------------------------------------------------------------------------------ 0 items found
Uncovered Expression Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.leading_zero_anticipator_I.leading_zero_counter_I Type name: leading_zero_counter File name: /home/mfertig/riscv2/riscv_FPU/external/riscv_bb/leading_zero_counter/leading_zero_counter.sv Number of uncovered expressions: 0 of 0 Number of unreachable expressions: 0 |
index | grade | line | expression ------------------------------------------------------------------------------------- 0 items found
Uncovered Toggle Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.leading_zero_anticipator_I.leading_zero_counter_I Type name: leading_zero_counter File name: /home/mfertig/riscv2/riscv_FPU/external/riscv_bb/leading_zero_counter/leading_zero_counter.sv Number of uncovered signal bits: 37 of 264 Number of unreachable signal bits: 0 Number of signal bits partially toggled(rise): 0 of 264 Number of signal bits partially toggled(fall): 0 of 264 |
Hit(Full) Hit(Rise) Hit(Fall) Signal ----------------------------------------------------------- 0 0 0 bitvector[17] 0 0 0 bitvector[16] 0 0 0 bitvector[15] 0 0 0 bitvector[14] 0 0 0 bitvector[13] 0 0 0 bitvector[12] 0 0 0 bitvector[11] 0 0 0 bitvector[10] 0 0 0 bitvector[9] 0 0 0 bitvector[8] 0 0 0 bitvector[7] 0 0 0 bitvector[6] 0 0 0 bitvector[5] 0 0 0 bitvector[4] 0 0 0 bitvector[3] 0 0 0 bitvector[2] 0 0 0 bitvector[1] 0 0 0 bitvector[0] 0 0 0 leading0s[7] 0 0 0 bitvector_enc[17] 0 0 0 bitvector_enc[16] 0 0 0 bitvector_enc[15] 0 0 0 bitvector_enc[14] 0 0 0 bitvector_enc[13] 0 0 0 bitvector_enc[12] 0 0 0 bitvector_enc[11] 0 0 0 bitvector_enc[10] 0 0 0 bitvector_enc[9] 0 0 0 bitvector_enc[8] 0 0 0 bitvector_enc[7] 0 0 0 bitvector_enc[6] 0 0 0 bitvector_enc[5] 0 0 0 bitvector_enc[4] 0 0 0 bitvector_enc[3] 0 0 0 bitvector_enc[2] 0 0 0 bitvector_enc[1] 0 0 0 bitvector_enc[0]
Uncovered Fsm Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.leading_zero_anticipator_I.leading_zero_counter_I Type name: leading_zero_counter File name: /home/mfertig/riscv2/riscv_FPU/external/riscv_bb/leading_zero_counter/leading_zero_counter.sv |
0 items found
Uncovered Assertion Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.leading_zero_anticipator_I.leading_zero_counter_I Type name: leading_zero_counter File name: /home/mfertig/riscv2/riscv_FPU/external/riscv_bb/leading_zero_counter/leading_zero_counter.sv Number of uncovered assertions: 0 of 0 |
Finished Failed Assertion Line Source Code ------------------------------------------------------------------------------------ 0 items found
Uncovered CoverGroup Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.leading_zero_anticipator_I.leading_zero_counter_I Type name: leading_zero_counter File name: /home/mfertig/riscv2/riscv_FPU/external/riscv_bb/leading_zero_counter/leading_zero_counter.sv Number of uncovered cover bins: 0 of 0 |
0 items found