Coverage Summary Report, Instance-Based
Top Level SummaryLegend and Help
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Instance name: tb_top.fma_top_I.adder_preliminary_I Type name: adder_preliminary File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/adder_preliminary.sv |
Coverage Summary Report, Instance-Based
| Overall | Overall Covered | Block | Expression | Toggle | FSM State | FSM Transition | Assertion | CoverGroup | CoverGroup Covered | name |
|---|---|---|---|---|---|---|---|---|---|---|
| 92.63% | 92.63% (767/828) | n/a | n/a | 92.63% (767/828) | n/a | n/a | n/a | n/a | n/a | adder_preliminary_I |
Uncovered Block Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.adder_preliminary_I Type name: adder_preliminary File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/adder_preliminary.sv Number of uncovered blocks: 0 of 0 Number of unreachable blocks: 0 |
Count Block Line Kind Origin Source Code ------------------------------------------------------------------------------ 0 items found
Uncovered Expression Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.adder_preliminary_I Type name: adder_preliminary File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/adder_preliminary.sv Number of uncovered expressions: 0 of 0 Number of unreachable expressions: 0 |
index | grade | line | expression ------------------------------------------------------------------------------------- 0 items found
Uncovered Toggle Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.adder_preliminary_I Type name: adder_preliminary File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/adder_preliminary.sv Number of uncovered signal bits: 61 of 828 Number of unreachable signal bits: 0 Number of signal bits partially toggled(rise): 0 of 828 Number of signal bits partially toggled(fall): 0 of 828 |
Hit(Full) Hit(Rise) Hit(Fall) Signal ----------------------------------------------------------- 0 0 0 carry_raw[164] 0 0 0 carry_raw[163] 0 0 0 carry_raw[162] 0 0 0 carry_raw[161] 0 0 0 carry_raw[160] 0 0 0 carry_raw[159] 0 0 0 carry_raw[158] 0 0 0 carry_raw[157] 0 0 0 carry_raw[156] 0 0 0 carry_raw[155] 0 0 0 carry_raw[154] 0 0 0 carry_raw[153] 0 0 0 carry_raw[152] 0 0 0 carry_raw[151] 0 0 0 carry_raw[150] 0 0 0 carry_raw[149] 0 0 0 carry_raw[148] 0 0 0 carry_raw[147] 0 0 0 carry_raw[146] 0 0 0 carry_raw[145] 0 0 0 carry_raw[144] 0 0 0 carry_raw[143] 0 0 0 carry_raw[142] 0 0 0 carry_raw[141] 0 0 0 carry_raw[140] 0 0 0 carry_raw[139] 0 0 0 carry_raw[138] 0 0 0 carry_raw[137] 0 0 0 carry_raw[136] 0 0 0 carry_raw[135] 0 0 0 carry_raw[134] 0 0 0 carry_raw[133] 0 0 0 carry_raw[132] 0 0 0 carry_raw[131] 0 0 0 carry_raw[130] 0 0 0 carry_raw[129] 0 0 0 carry_raw[128] 0 0 0 carry_raw[127] 0 0 0 carry_raw[126] 0 0 0 carry_raw[125] 0 0 0 carry_raw[124] 0 0 0 carry_raw[123] 0 0 0 carry_raw[122] 0 0 0 carry_raw[121] 0 0 0 carry_raw[120] 0 0 0 carry_raw[119] 0 0 0 carry_raw[118] 0 0 0 carry_raw[117] 0 0 0 carry_raw[116] 0 0 0 carry_raw[115] 0 0 0 carry_raw[114] 0 0 0 carry_raw[113] 0 0 0 carry_raw[112] 0 0 0 carry_raw[111] 0 0 0 carry_raw[110] 0 0 0 carry_raw[3] 0 0 0 carry_raw[2] 0 0 0 carry_raw[1] 0 0 0 carry_raw[0] 0 0 0 result_raw[163] 0 0 0 result_uncut[164]
Uncovered Fsm Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.adder_preliminary_I Type name: adder_preliminary File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/adder_preliminary.sv |
0 items found
Uncovered Assertion Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.adder_preliminary_I Type name: adder_preliminary File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/adder_preliminary.sv Number of uncovered assertions: 0 of 0 |
Finished Failed Assertion Line Source Code ------------------------------------------------------------------------------------ 0 items found
Uncovered CoverGroup Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.adder_preliminary_I Type name: adder_preliminary File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/adder_preliminary.sv Number of uncovered cover bins: 0 of 0 |
0 items found