Coverage Summary Report, Instance-Based
Top Level SummaryLegend and Help
Instance name: tb_top.fma_top_I.compressor_row_3_2_I.genblk1[5].comp_3_2_I Type name: comp_3_2 File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/csa_tree/comp_3_2.v |
Coverage Summary Report, Instance-Based
Overall | Overall Covered | Block | Expression | Toggle | FSM State | FSM Transition | Assertion | CoverGroup | CoverGroup Covered | name |
---|---|---|---|---|---|---|---|---|---|---|
90.00% | 83.33% (5/6) | 100.00% (1/1) | n/a | 80.00% (4/5) | n/a | n/a | n/a | n/a | n/a | comp_3_2_I |
Uncovered Block Detail Report, Instance Based
Instance name: tb_top.fma_top_I.compressor_row_3_2_I.genblk1[5].comp_3_2_I Type name: comp_3_2 File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/csa_tree/comp_3_2.v Number of uncovered blocks: 0 of 1 Number of unreachable blocks: 0 |
Count Block Line Kind Origin Source Code ------------------------------------------------------------------------------ 0 items found
Uncovered Expression Detail Report, Instance Based
Instance name: tb_top.fma_top_I.compressor_row_3_2_I.genblk1[5].comp_3_2_I Type name: comp_3_2 File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/csa_tree/comp_3_2.v Number of uncovered expressions: 0 of 0 Number of unreachable expressions: 0 |
index | grade | line | expression ------------------------------------------------------------------------------------- 0 items found
Uncovered Toggle Detail Report, Instance Based
Instance name: tb_top.fma_top_I.compressor_row_3_2_I.genblk1[5].comp_3_2_I Type name: comp_3_2 File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/csa_tree/comp_3_2.v Number of uncovered signal bits: 1 of 5 Number of unreachable signal bits: 0 Number of signal bits partially toggled(rise): 0 of 5 Number of signal bits partially toggled(fall): 0 of 5 |
Hit(Full) Hit(Rise) Hit(Fall) Signal ----------------------------------------------------------- 0 0 0 comp_in[1]
Uncovered Fsm Detail Report, Instance Based
Instance name: tb_top.fma_top_I.compressor_row_3_2_I.genblk1[5].comp_3_2_I Type name: comp_3_2 File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/csa_tree/comp_3_2.v |
0 items found
Uncovered Assertion Detail Report, Instance Based
Instance name: tb_top.fma_top_I.compressor_row_3_2_I.genblk1[5].comp_3_2_I Type name: comp_3_2 File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/csa_tree/comp_3_2.v Number of uncovered assertions: 0 of 0 |
Finished Failed Assertion Line Source Code ------------------------------------------------------------------------------------ 0 items found
Uncovered CoverGroup Detail Report, Instance Based
Instance name: tb_top.fma_top_I.compressor_row_3_2_I.genblk1[5].comp_3_2_I Type name: comp_3_2 File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/csa_tree/comp_3_2.v Number of uncovered cover bins: 0 of 0 |
0 items found