Coverage Summary Report, Instance-Based
Top Level SummaryLegend and Help
|
Instance name: tb_top.fma_top_I.compressor_row_3_2_I Type name: compressor_row_3_2 File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/compressor_row_3_2.sv |
Coverage Summary Report, Instance-Based
| Overall | Overall Covered | Block | Expression | Toggle | FSM State | FSM Transition | Assertion | CoverGroup | CoverGroup Covered | name |
|---|---|---|---|---|---|---|---|---|---|---|
| 98.44% | 98.44% (633/643) | n/a | n/a | 98.44% (633/643) | n/a | n/a | n/a | n/a | n/a | compressor_row_3_2_I |
Uncovered Block Detail Report, Instance Based
|
Instance name: tb_top.fma_top_I.compressor_row_3_2_I Type name: compressor_row_3_2 File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/compressor_row_3_2.sv Number of uncovered blocks: 0 of 0 Number of unreachable blocks: 0 |
Count Block Line Kind Origin Source Code ------------------------------------------------------------------------------ 0 items found
Uncovered Expression Detail Report, Instance Based
|
Instance name: tb_top.fma_top_I.compressor_row_3_2_I Type name: compressor_row_3_2 File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/compressor_row_3_2.sv Number of uncovered expressions: 0 of 0 Number of unreachable expressions: 0 |
index | grade | line | expression ------------------------------------------------------------------------------------- 0 items found
Uncovered Toggle Detail Report, Instance Based
|
Instance name: tb_top.fma_top_I.compressor_row_3_2_I Type name: compressor_row_3_2 File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/compressor_row_3_2.sv Number of uncovered signal bits: 10 of 643 Number of unreachable signal bits: 0 Number of signal bits partially toggled(rise): 0 of 643 Number of signal bits partially toggled(fall): 0 of 643 |
Hit(Full) Hit(Rise) Hit(Fall) Signal ----------------------------------------------------------- 0 0 0 comp_tree_sum[106] 0 0 0 comp_tree_carry[106] 0 0 0 comp_tree_carry[5] 0 0 0 comp_tree_carry[4] 0 0 0 comp_tree_carry[3] 0 0 0 comp_tree_carry[2] 0 0 0 comp_tree_carry[1] 0 0 0 comp_tree_carry[0] 0 0 0 carry_raw[0] 0 0 0 carry_shifted[106]
Uncovered Fsm Detail Report, Instance Based
|
Instance name: tb_top.fma_top_I.compressor_row_3_2_I Type name: compressor_row_3_2 File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/compressor_row_3_2.sv |
0 items found
Uncovered Assertion Detail Report, Instance Based
|
Instance name: tb_top.fma_top_I.compressor_row_3_2_I Type name: compressor_row_3_2 File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/compressor_row_3_2.sv Number of uncovered assertions: 0 of 0 |
Finished Failed Assertion Line Source Code ------------------------------------------------------------------------------------ 0 items found
Uncovered CoverGroup Detail Report, Instance Based
|
Instance name: tb_top.fma_top_I.compressor_row_3_2_I Type name: compressor_row_3_2 File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/compressor_row_3_2.sv Number of uncovered cover bins: 0 of 0 |
0 items found