Coverage Summary Report, Instance-Based
Top Level SummaryLegend and Help
Instance name: tb_top.fma_top_I Type name: fma_top File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/fma_top.sv |
Coverage Summary Report, Instance-Based
Overall | Overall Covered | Block | Expression | Toggle | FSM State | FSM Transition | Assertion | CoverGroup | CoverGroup Covered | name |
---|---|---|---|---|---|---|---|---|---|---|
96.36% | 92.73% (2706/2918) | 100.00% (6/6) | n/a | 92.72% (2700/2912) | n/a | n/a | n/a | n/a | n/a | fma_top_I |
Uncovered Block Detail Report, Instance Based
Instance name: tb_top.fma_top_I Type name: fma_top File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/fma_top.sv Number of uncovered blocks: 0 of 6 Number of unreachable blocks: 0 |
Count Block Line Kind Origin Source Code ------------------------------------------------------------------------------ 0 items found
Uncovered Expression Detail Report, Instance Based
Instance name: tb_top.fma_top_I Type name: fma_top File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/fma_top.sv Number of uncovered expressions: 0 of 0 Number of unreachable expressions: 0 |
index | grade | line | expression ------------------------------------------------------------------------------------- 0 items found
Uncovered Toggle Detail Report, Instance Based
Instance name: tb_top.fma_top_I Type name: fma_top File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/fma_top.sv Number of uncovered signal bits: 212 of 2912 Number of unreachable signal bits: 0 Number of signal bits partially toggled(rise): 1 of 2912 Number of signal bits partially toggled(fall): 0 of 2912 |
Hit(Full) Hit(Rise) Hit(Fall) Signal ----------------------------------------------------------- 0 1 0 res_n 0 0 0 exception_flags[3] 0 0 0 comp_tree_carry_mult_active[127] 0 0 0 comp_tree_carry_mult_active[126] 0 0 0 comp_tree_carry_mult_active[125] 0 0 0 comp_tree_carry_mult_active[124] 0 0 0 comp_tree_carry_mult_active[123] 0 0 0 comp_tree_carry_mult_active[122] 0 0 0 comp_tree_carry_mult_active[121] 0 0 0 comp_tree_carry_mult_active[120] 0 0 0 comp_tree_carry_mult_active[119] 0 0 0 comp_tree_carry_mult_active[118] 0 0 0 comp_tree_carry_mult_active[117] 0 0 0 comp_tree_carry_mult_active[116] 0 0 0 comp_tree_carry_mult_active[115] 0 0 0 comp_tree_carry_mult_active[114] 0 0 0 comp_tree_carry_mult_active[113] 0 0 0 comp_tree_carry_mult_active[112] 0 0 0 comp_tree_carry_mult_active[111] 0 0 0 comp_tree_carry_mult_active[110] 0 0 0 comp_tree_carry_mult_active[109] 0 0 0 comp_tree_carry_mult_active[108] 0 0 0 comp_tree_carry_mult_active[107] 0 0 0 comp_tree_carry_mult_active[5] 0 0 0 comp_tree_carry_mult_active[4] 0 0 0 comp_tree_carry_mult_active[3] 0 0 0 comp_tree_carry_mult_active[2] 0 0 0 comp_tree_carry_mult_active[1] 0 0 0 comp_tree_carry_mult_active[0] 0 0 0 comp_tree_sum_mult_active[127] 0 0 0 comp_tree_sum_mult_active[126] 0 0 0 comp_tree_sum_mult_active[125] 0 0 0 comp_tree_sum_mult_active[124] 0 0 0 comp_tree_sum_mult_active[123] 0 0 0 comp_tree_sum_mult_active[122] 0 0 0 comp_tree_sum_mult_active[121] 0 0 0 comp_tree_sum_mult_active[120] 0 0 0 comp_tree_sum_mult_active[119] 0 0 0 comp_tree_sum_mult_active[118] 0 0 0 comp_tree_sum_mult_active[117] 0 0 0 comp_tree_sum_mult_active[116] 0 0 0 comp_tree_sum_mult_active[115] 0 0 0 comp_tree_sum_mult_active[114] 0 0 0 comp_tree_sum_mult_active[113] 0 0 0 comp_tree_sum_mult_active[112] 0 0 0 comp_tree_sum_mult_active[111] 0 0 0 comp_tree_sum_mult_active[110] 0 0 0 comp_tree_sum_mult_active[109] 0 0 0 comp_tree_sum_mult_active[108] 0 0 0 comp_tree_sum_mult_active[107] 0 0 0 comp_tree_carry[127] 0 0 0 comp_tree_carry[126] 0 0 0 comp_tree_carry[125] 0 0 0 comp_tree_carry[124] 0 0 0 comp_tree_carry[123] 0 0 0 comp_tree_carry[122] 0 0 0 comp_tree_carry[121] 0 0 0 comp_tree_carry[120] 0 0 0 comp_tree_carry[119] 0 0 0 comp_tree_carry[118] 0 0 0 comp_tree_carry[117] 0 0 0 comp_tree_carry[116] 0 0 0 comp_tree_carry[115] 0 0 0 comp_tree_carry[114] 0 0 0 comp_tree_carry[113] 0 0 0 comp_tree_carry[112] 0 0 0 comp_tree_carry[111] 0 0 0 comp_tree_carry[110] 0 0 0 comp_tree_carry[109] 0 0 0 comp_tree_carry[108] 0 0 0 comp_tree_carry[107] 0 0 0 comp_tree_carry[5] 0 0 0 comp_tree_carry[4] 0 0 0 comp_tree_carry[3] 0 0 0 comp_tree_carry[2] 0 0 0 comp_tree_carry[1] 0 0 0 comp_tree_carry[0] 0 0 0 comp_tree_sum[127] 0 0 0 comp_tree_sum[126] 0 0 0 comp_tree_sum[125] 0 0 0 comp_tree_sum[124] 0 0 0 comp_tree_sum[123] 0 0 0 comp_tree_sum[122] 0 0 0 comp_tree_sum[121] 0 0 0 comp_tree_sum[120] 0 0 0 comp_tree_sum[119] 0 0 0 comp_tree_sum[118] 0 0 0 comp_tree_sum[117] 0 0 0 comp_tree_sum[116] 0 0 0 comp_tree_sum[115] 0 0 0 comp_tree_sum[114] 0 0 0 comp_tree_sum[113] 0 0 0 comp_tree_sum[112] 0 0 0 comp_tree_sum[111] 0 0 0 comp_tree_sum[110] 0 0 0 comp_tree_sum[109] 0 0 0 comp_tree_sum[108] 0 0 0 comp_tree_sum[107] 0 0 0 carry_raw[0] 0 0 0 result_raw[163] 0 0 0 ros_exception_flags[3] 0 0 0 stage_0_rm[3] 0 0 0 stage_0_comp_tree_carry[127] 0 0 0 stage_0_comp_tree_carry[126] 0 0 0 stage_0_comp_tree_carry[125] 0 0 0 stage_0_comp_tree_carry[124] 0 0 0 stage_0_comp_tree_carry[123] 0 0 0 stage_0_comp_tree_carry[122] 0 0 0 stage_0_comp_tree_carry[121] 0 0 0 stage_0_comp_tree_carry[120] 0 0 0 stage_0_comp_tree_carry[119] 0 0 0 stage_0_comp_tree_carry[118] 0 0 0 stage_0_comp_tree_carry[117] 0 0 0 stage_0_comp_tree_carry[116] 0 0 0 stage_0_comp_tree_carry[115] 0 0 0 stage_0_comp_tree_carry[114] 0 0 0 stage_0_comp_tree_carry[113] 0 0 0 stage_0_comp_tree_carry[112] 0 0 0 stage_0_comp_tree_carry[111] 0 0 0 stage_0_comp_tree_carry[110] 0 0 0 stage_0_comp_tree_carry[109] 0 0 0 stage_0_comp_tree_carry[108] 0 0 0 stage_0_comp_tree_carry[107] 0 0 0 stage_0_comp_tree_carry[106] 0 0 0 stage_0_comp_tree_carry[5] 0 0 0 stage_0_comp_tree_carry[4] 0 0 0 stage_0_comp_tree_carry[3] 0 0 0 stage_0_comp_tree_carry[2] 0 0 0 stage_0_comp_tree_carry[1] 0 0 0 stage_0_comp_tree_carry[0] 0 0 0 stage_0_comp_tree_sum[127] 0 0 0 stage_0_comp_tree_sum[126] 0 0 0 stage_0_comp_tree_sum[125] 0 0 0 stage_0_comp_tree_sum[124] 0 0 0 stage_0_comp_tree_sum[123] 0 0 0 stage_0_comp_tree_sum[122] 0 0 0 stage_0_comp_tree_sum[121] 0 0 0 stage_0_comp_tree_sum[120] 0 0 0 stage_0_comp_tree_sum[119] 0 0 0 stage_0_comp_tree_sum[118] 0 0 0 stage_0_comp_tree_sum[117] 0 0 0 stage_0_comp_tree_sum[116] 0 0 0 stage_0_comp_tree_sum[115] 0 0 0 stage_0_comp_tree_sum[114] 0 0 0 stage_0_comp_tree_sum[113] 0 0 0 stage_0_comp_tree_sum[112] 0 0 0 stage_0_comp_tree_sum[111] 0 0 0 stage_0_comp_tree_sum[110] 0 0 0 stage_0_comp_tree_sum[109] 0 0 0 stage_0_comp_tree_sum[108] 0 0 0 stage_0_comp_tree_sum[107] 0 0 0 stage_0_comp_tree_sum[106] 0 0 0 adder_carry_raw[164] 0 0 0 adder_carry_raw[163] 0 0 0 adder_carry_raw[162] 0 0 0 adder_carry_raw[161] 0 0 0 adder_carry_raw[160] 0 0 0 adder_carry_raw[159] 0 0 0 adder_carry_raw[158] 0 0 0 adder_carry_raw[157] 0 0 0 adder_carry_raw[156] 0 0 0 adder_carry_raw[155] 0 0 0 adder_carry_raw[154] 0 0 0 adder_carry_raw[153] 0 0 0 adder_carry_raw[152] 0 0 0 adder_carry_raw[151] 0 0 0 adder_carry_raw[150] 0 0 0 adder_carry_raw[149] 0 0 0 adder_carry_raw[148] 0 0 0 adder_carry_raw[147] 0 0 0 adder_carry_raw[146] 0 0 0 adder_carry_raw[145] 0 0 0 adder_carry_raw[144] 0 0 0 adder_carry_raw[143] 0 0 0 adder_carry_raw[142] 0 0 0 adder_carry_raw[141] 0 0 0 adder_carry_raw[140] 0 0 0 adder_carry_raw[139] 0 0 0 adder_carry_raw[138] 0 0 0 adder_carry_raw[137] 0 0 0 adder_carry_raw[136] 0 0 0 adder_carry_raw[135] 0 0 0 adder_carry_raw[134] 0 0 0 adder_carry_raw[133] 0 0 0 adder_carry_raw[132] 0 0 0 adder_carry_raw[131] 0 0 0 adder_carry_raw[130] 0 0 0 adder_carry_raw[129] 0 0 0 adder_carry_raw[128] 0 0 0 adder_carry_raw[127] 0 0 0 adder_carry_raw[126] 0 0 0 adder_carry_raw[125] 0 0 0 adder_carry_raw[124] 0 0 0 adder_carry_raw[123] 0 0 0 adder_carry_raw[122] 0 0 0 adder_carry_raw[121] 0 0 0 adder_carry_raw[120] 0 0 0 adder_carry_raw[119] 0 0 0 adder_carry_raw[118] 0 0 0 adder_carry_raw[117] 0 0 0 adder_carry_raw[116] 0 0 0 adder_carry_raw[115] 0 0 0 adder_carry_raw[114] 0 0 0 adder_carry_raw[113] 0 0 0 adder_carry_raw[112] 0 0 0 adder_carry_raw[111] 0 0 0 adder_carry_raw[110] 0 0 0 adder_carry_raw[3] 0 0 0 adder_carry_raw[2] 0 0 0 adder_carry_raw[1] 0 0 0 adder_carry_raw[0] 0 0 0 stage_1_result_raw[163]
Uncovered Fsm Detail Report, Instance Based
Instance name: tb_top.fma_top_I Type name: fma_top File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/fma_top.sv |
0 items found
Uncovered Assertion Detail Report, Instance Based
Instance name: tb_top.fma_top_I Type name: fma_top File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/fma_top.sv Number of uncovered assertions: 0 of 0 |
Finished Failed Assertion Line Source Code ------------------------------------------------------------------------------------ 0 items found
Uncovered CoverGroup Detail Report, Instance Based
Instance name: tb_top.fma_top_I Type name: fma_top File name: /home/mfertig/riscv2/riscv_FPU/modules/fma/fma_top.sv Number of uncovered cover bins: 0 of 0 |
0 items found