Coverage Summary Report, Instance-Based
Top Level SummaryLegend and Help
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Instance name: tb_top Type name: tb_top File name: /home/mfertig/riscv2/riscv_FPU/verification/fpu/tb/fma/src/tb_top.sv |
Coverage Summary Report, Instance-Based
| Overall | Overall Covered | Block | Expression | Toggle | FSM State | FSM Transition | Assertion | CoverGroup | CoverGroup Covered | name |
|---|---|---|---|---|---|---|---|---|---|---|
| 99.82% | 99.28% (276/278) | 100.00% (4/4) | n/a | 99.27% (271/273) | n/a | n/a | 100.00% (1/1) | n/a | n/a | tb_top |
Uncovered Block Detail Report, Instance Based
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Instance name: tb_top Type name: tb_top File name: /home/mfertig/riscv2/riscv_FPU/verification/fpu/tb/fma/src/tb_top.sv Number of uncovered blocks: 0 of 4 Number of unreachable blocks: 0 |
Count Block Line Kind Origin Source Code ------------------------------------------------------------------------------ 0 items found
Uncovered Expression Detail Report, Instance Based
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Instance name: tb_top Type name: tb_top File name: /home/mfertig/riscv2/riscv_FPU/verification/fpu/tb/fma/src/tb_top.sv Number of uncovered expressions: 0 of 0 Number of unreachable expressions: 0 |
index | grade | line | expression ------------------------------------------------------------------------------------- 0 items found
Uncovered Toggle Detail Report, Instance Based
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Instance name: tb_top Type name: tb_top File name: /home/mfertig/riscv2/riscv_FPU/verification/fpu/tb/fma/src/tb_top.sv Number of uncovered signal bits: 2 of 273 Number of unreachable signal bits: 0 Number of signal bits partially toggled(rise): 1 of 273 Number of signal bits partially toggled(fall): 0 of 273 |
Hit(Full) Hit(Rise) Hit(Fall) Signal ----------------------------------------------------------- 0 1 0 res_n 0 0 0 exceptionFlags[3]
Uncovered Fsm Detail Report, Instance Based
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Instance name: tb_top Type name: tb_top File name: /home/mfertig/riscv2/riscv_FPU/verification/fpu/tb/fma/src/tb_top.sv |
0 items found
Uncovered Assertion Detail Report, Instance Based
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Instance name: tb_top Type name: tb_top File name: /home/mfertig/riscv2/riscv_FPU/verification/fpu/tb/fma/src/tb_top.sv Number of uncovered assertions: 0 of 1 |
Finished Failed Assertion Line Source Code ------------------------------------------------------------------------------------
Uncovered CoverGroup Detail Report, Instance Based
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Instance name: tb_top Type name: tb_top File name: /home/mfertig/riscv2/riscv_FPU/verification/fpu/tb/fma/src/tb_top.sv Number of uncovered cover bins: 0 of 0 |
0 items found