VERIGEN_FREE/ 0000775 0001750 0001750 00000000000 13377751243 012650 5 ustar mfertig mfertig VERIGEN_FREE/README 0000664 0001750 0001750 00000000304 13376012552 013515 0 ustar mfertig mfertig Try 'verigen_free -f simple_mem2.cfg' ...
... to create SIMPLE_MEM2_tb.v SIMPLE_MEM2.v
Try ./irun.sh
... to start simulation in a Cadence environment, otherwise use your own Verilog simulator
VERIGEN_FREE/mesi/ 0000775 0001750 0001750 00000000000 13377751300 013577 5 ustar mfertig mfertig VERIGEN_FREE/mesi/MESI.v 0000664 0001750 0001750 00000025553 13377777573 014561 0 ustar mfertig mfertig // generated by verigen.pl on Thu Nov 29 16:02:07 2018
// input file: mesi.cfg
module MESI(
clk, res_n, addr, cp, rd, wr, // inputs
mesi, index // outputs
);
input wire clk;
input wire res_n;
input wire [31:0] addr;
input wire cp;
input wire rd;
input wire wr;
output reg [3:0] mesi;
output reg [5:0] index;
//
// parameter constants
//---------------------------
parameter ZERO = 4'b0000;
parameter ZERO_ADDR = 6'b000000;
parameter MODIFIED = 4'b1000;
parameter EXCLUSIVE = 4'b0100;
parameter SHARED = 4'b0010;
parameter INVALID = 4'b0001;
//
// state encoding constants
//---------------------------
parameter [2:0] ID = 3'b000;
parameter [2:0] RD = 3'b001;
parameter [2:0] WR = 3'b010;
parameter [2:0] rRD = 3'b101;
parameter [2:0] rWR = 3'b110;
reg [2:0] STATE, NEXT_STATE;
//
// memory instantiations
//---------------------------
wire MESI_RAM_clk;
wire MESI_RAM_res;
reg MESI_RAM_wr;
reg [5:0] MESI_RAM_wr_addr;
reg [3:0] MESI_RAM_wr_data;
reg MESI_RAM_rd;
reg [5:0] MESI_RAM_rd_addr;
reg MESI_RAM_status;
wire [3:0] MESI_RAM_rd_data;
assign MESI_RAM_clk = clk;
assign MESI_RAM_res_n = res_n;
RAM #(4,64) MESI_RAM(.clk(MESI_RAM_clk), .res_n(MESI_RAM_res),
.wr(MESI_RAM_wr), .wr_addr(MESI_RAM_wr_addr[5:0]), .wr_data(MESI_RAM_wr_data[3:0]),
.rd(MESI_RAM_rd), .rd_addr(MESI_RAM_rd_addr[5:0]), .rd_data(MESI_RAM_rd_data[3:0]) );
wire TAG_RAM_clk;
wire TAG_RAM_res;
reg TAG_RAM_wr;
reg [5:0] TAG_RAM_wr_addr;
reg [23:0] TAG_RAM_wr_data;
reg TAG_RAM_rd;
reg [5:0] TAG_RAM_rd_addr;
reg TAG_RAM_status;
wire [23:0] TAG_RAM_rd_data;
assign TAG_RAM_clk = clk;
assign TAG_RAM_res_n = res_n;
RAM #(24,64) TAG_RAM(.clk(TAG_RAM_clk), .res_n(TAG_RAM_res),
.wr(TAG_RAM_wr), .wr_addr(TAG_RAM_wr_addr[5:0]), .wr_data(TAG_RAM_wr_data[23:0]),
.rd(TAG_RAM_rd), .rd_addr(TAG_RAM_rd_addr[5:0]), .rd_data(TAG_RAM_rd_data[23:0]) );
//
// constant expressions
//---------------------------
wire IDLE; assign IDLE = ~res_n | (~rd & ~wr);
wire IS_EXCLUSIVE; assign IS_EXCLUSIVE = POP_MESI_RAM(addr[7:2])==EXCLUSIVE;
wire IS_INVALID; assign IS_INVALID = POP_MESI_RAM(addr[7:2])==INVALID;
wire IS_MODIFIED; assign IS_MODIFIED = POP_MESI_RAM(addr[7:2])==MODIFIED;
wire IS_SHARED; assign IS_SHARED = POP_MESI_RAM(addr[7:2])==SHARED;
wire MESI_IS_ZERO; assign MESI_IS_ZERO = POP_MESI_RAM(addr[7:2])==ZERO;
wire READ; assign READ = res_n & cp & rd;
wire TAG_MATCH; assign TAG_MATCH = POP_TAG_RAM(addr[7:2])==addr[31:8];
wire WRITE; assign WRITE = res_n & cp & wr;
wire rREAD; assign rREAD = res_n & ~cp & rd;
wire rWRITE; assign rWRITE = res_n & ~cp & wr;
//
// initials for simulator
//---------------------------
initial begin
STATE <= ID;
MESI_RAM_wr <= 1'b0;
MESI_RAM_wr_addr <= {5{1'b0}};
MESI_RAM_wr_data <= {3{1'b0}};
MESI_RAM_rd <= 1'b0;
MESI_RAM_rd_addr <= {5{1'b0}};
MESI_RAM_status <= 1'b0;
TAG_RAM_wr <= 1'b0;
TAG_RAM_wr_addr <= {5{1'b0}};
TAG_RAM_wr_data <= {23{1'b0}};
TAG_RAM_rd <= 1'b0;
TAG_RAM_rd_addr <= {5{1'b0}};
TAG_RAM_status <= 1'b0;
end
//
// state transfer
//---------------------------
always @( posedge clk or negedge res_n) begin
if( ~res_n ) begin
STATE <= ID;
end else begin
STATE <= NEXT_STATE;
end // if
end // always@
always @( * ) begin
case ( STATE )
ID : begin
if ( IDLE ) begin
NEXT_STATE <= ID;
// MEMORY action ...
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
MESI_RAM_status <= NOP_MESI_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=ZERO;
index<=addr[7:2];
end
if ( READ & TAG_MATCH & ~MESI_IS_ZERO ) begin
NEXT_STATE <= RD;
// MEMORY action ...
MESI_RAM_status <= PUSH_MESI_RAM(addr[7:2],EXCLUSIVE);
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=EXCLUSIVE;
index<=addr[7:2];
end
if ( READ & ( ~TAG_MATCH | MESI_IS_ZERO ) ) begin
NEXT_STATE <= RD;
// MEMORY action ...
MESI_RAM_status <= PUSH_MESI_RAM(addr[7:2],EXCLUSIVE);
TAG_RAM_status <= PUSH_TAG_RAM(addr[7:2],addr[31:8]);
// MEALY output action ...
mesi<=EXCLUSIVE;
index<=addr[7:2];
end
if ( WRITE & TAG_MATCH ) begin
NEXT_STATE <= WR;
// MEMORY action ...
MESI_RAM_status <= PUSH_MESI_RAM(addr[7:2],MODIFIED);
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=MODIFIED;
index<=addr[7:2];
end
if ( rWRITE & TAG_MATCH ) begin
NEXT_STATE <= rWR;
// MEMORY action ...
MESI_RAM_status <= PUSH_MESI_RAM(addr[7:2],INVALID);
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=INVALID;
index<=addr[7:2];
end
if ( rREAD & TAG_MATCH ) begin
NEXT_STATE <= rRD;
// MEMORY action ...
MESI_RAM_status <= PUSH_MESI_RAM(addr[7:2],SHARED);
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=SHARED;
index<=addr[7:2];
end
if ( rREAD & ~TAG_MATCH ) begin
NEXT_STATE <= ID;
// MEMORY action ...
MESI_RAM_status <= NOP_MESI_RAM(1'b0,ZERO_ADDR);
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=ZERO;
index<=addr[7:2];
end
end // ID
RD : begin
if ( IDLE ) begin
NEXT_STATE <= ID;
// MEMORY action ...
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
MESI_RAM_status <= NOP_MESI_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=ZERO;
end
if ( READ & TAG_MATCH & ~MESI_IS_ZERO ) begin
NEXT_STATE <= RD;
// MEMORY action ...
MESI_RAM_status <= PUSH_MESI_RAM(addr[7:2],EXCLUSIVE);
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=EXCLUSIVE;
index<=addr[7:2];
end
if ( READ & (~TAG_MATCH | MESI_IS_ZERO) ) begin
NEXT_STATE <= RD;
// MEMORY action ...
MESI_RAM_status <= PUSH_MESI_RAM(addr[7:2],EXCLUSIVE);
TAG_RAM_status <= PUSH_TAG_RAM(addr[7:2],addr[31:8]);
// MEALY output action ...
mesi<=EXCLUSIVE;
index<=addr[7:2];
end
end // RD
WR : begin
if ( IDLE ) begin
NEXT_STATE <= ID;
// MEMORY action ...
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
MESI_RAM_status <= NOP_MESI_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=ZERO;
index<=addr[7:2];
end
if ( WRITE & TAG_MATCH ) begin
NEXT_STATE <= WR;
// MEMORY action ...
MESI_RAM_status <= PUSH_MESI_RAM(addr[7:2],MODIFIED);
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=MODIFIED;
index<=addr[7:2];
end
if ( WRITE & ~TAG_MATCH ) begin
NEXT_STATE <= ID;
// MEMORY action ...
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
MESI_RAM_status <= NOP_MESI_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=ZERO;
index<=addr[7:2];
end
end // WR
rRD : begin
if ( IDLE ) begin
NEXT_STATE <= ID;
// MEMORY action ...
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
MESI_RAM_status <= NOP_MESI_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=ZERO;
index<=addr[7:2];
end
if ( rREAD & TAG_MATCH & ~MESI_IS_ZERO ) begin
NEXT_STATE <= rRD;
// MEMORY action ...
MESI_RAM_status <= PUSH_MESI_RAM(addr[7:2],SHARED);
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=SHARED;
index<=addr[7:2];
end
if ( rREAD & ( ~TAG_MATCH | ( TAG_MATCH & MESI_IS_ZERO ) ) ) begin
NEXT_STATE <= ID;
// MEMORY action ...
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
MESI_RAM_status <= NOP_MESI_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=ZERO;
index<=addr[7:2];
end
end // rRD
rWR : begin
if ( IDLE ) begin
NEXT_STATE <= ID;
// MEMORY action ...
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
MESI_RAM_status <= NOP_MESI_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=ZERO;
index<=addr[7:2];
end
if ( rWRITE & TAG_MATCH & ~MESI_IS_ZERO ) begin
NEXT_STATE <= rWR;
// MEMORY action ...
MESI_RAM_status <= PUSH_MESI_RAM(addr[7:2],INVALID);
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=INVALID;
index<=addr[7:2];
end
if ( rWRITE & ~TAG_MATCH | (TAG_MATCH & MESI_IS_ZERO) ) begin
NEXT_STATE <= rWR;
// MEMORY action ...
MESI_RAM_status <= NOP_MESI_RAM(1'b0,ZERO_ADDR);
TAG_RAM_status <= NOP_TAG_RAM(1'b0,ZERO_ADDR);
// MEALY output action ...
mesi<=ZERO;
index<=addr[7:2];
end
end // rWR
default begin
NEXT_STATE <= ID;
mesi[3:0] <= {4{1'b0}};
index[5:0] <= {6{1'b0}};
end
endcase
end // always@
//
// memory functions
//---------------------------
function [3:0] POP_MESI_RAM;
input [5:0] rd_addr;
begin
MESI_RAM_rd = 1'b1;
MESI_RAM_rd_addr = rd_addr;
POP_MESI_RAM = MESI_RAM_rd_data;
end
endfunction
function PUSH_MESI_RAM;
input [5:0] wr_addr;
input [3:0] wr_data;
begin
MESI_RAM_wr = 1'b1;
MESI_RAM_wr_addr = wr_addr;
MESI_RAM_wr_data = wr_data;
PUSH_MESI_RAM = 1'b1;
end
endfunction
function TOP_MESI_RAM;
input [5:0] rd_addr;
begin
MESI_RAM_rd = 1'b1;
MESI_RAM_rd_addr = rd_addr;
TOP_MESI_RAM = MESI_RAM_rd_data;
end
endfunction
function NOP_MESI_RAM;
input wr;
input [5:0] wr_addr;
begin
//MESI_RAM_rd = 1'b0;
MESI_RAM_wr = wr;
MESI_RAM_wr_addr = wr_addr;
MESI_RAM_wr_data = {4{1'b0}};
NOP_MESI_RAM = 1'b1;
end
endfunction
function [23:0] POP_TAG_RAM;
input [5:0] rd_addr;
begin
TAG_RAM_rd = 1'b1;
TAG_RAM_rd_addr = rd_addr;
POP_TAG_RAM = TAG_RAM_rd_data;
end
endfunction
function PUSH_TAG_RAM;
input [5:0] wr_addr;
input [23:0] wr_data;
begin
TAG_RAM_wr = 1'b1;
TAG_RAM_wr_addr = wr_addr;
TAG_RAM_wr_data = wr_data;
PUSH_TAG_RAM = 1'b1;
end
endfunction
function TOP_TAG_RAM;
input [5:0] rd_addr;
begin
TAG_RAM_rd = 1'b1;
TAG_RAM_rd_addr = rd_addr;
TOP_TAG_RAM = TAG_RAM_rd_data;
end
endfunction
function NOP_TAG_RAM;
input wr;
input [5:0] wr_addr;
begin
//TAG_RAM_rd = 1'b0;
TAG_RAM_wr = wr;
TAG_RAM_wr_addr = wr_addr;
TAG_RAM_wr_data = {24{1'b0}};
NOP_TAG_RAM = 1'b1;
end
endfunction
endmodule
//
// memory
//---------------------------
module RAM ( clk, res_n, wr, wr_addr, wr_data, rd, rd_addr, rd_data );
parameter data_width = 32;
parameter entries = 16;
parameter addr_width = $clog2(entries);
input wire clk, res_n, rd, wr;
input wire [data_width-1:0] wr_data;
input wire [addr_width-1:0] rd_addr, wr_addr;
output wire [data_width-1:0] rd_data;
parameter ZERO_ADDR = {addr_width{1'b0}};
parameter ZERO_DATA = {data_width{1'b0}};
parameter ONE_DATA = {data_width{1'b1}};
reg [data_width-1:0] MEMORY [entries-1:0];
integer i;
initial begin
// Clear RAM before simulation start
for ( i = 0; i < entries; i = i + 1 ) begin
MEMORY[ i ] <= ZERO_DATA;
end
end
// IN-CYCLE READ ACCESS
assign rd_data = {data_width{rd & res_n}} & MEMORY[rd_addr];
always @ ( posedge clk ) begin
// WRITE ACCESS
MEMORY[wr_addr] <= {data_width{wr & res_n}} & wr_data;
end
endmodule
VERIGEN_FREE/mesi/mesi.cfg 0000664 0001750 0001750 00000017116 13377757543 015242 0 ustar mfertig mfertig
MESI
mealy
clk
res_n
addr[31:0]
cp
rd
wr
mesi[3:0]
index[5:0]
clk
res_n
clk,posedge
res_n,negedge
man
ID,000
RD,001
WR,010
rRD,101
rWR,110
//
// is ended by
// has the format src_state, transition_condition, tgt_state, set_output, memory_op
//
// transition_condition could contain a compare on memory data like
// POP_MY_RAM(my_addr) to transfer to another state
//
// memory_op has the format [PUSH|POP|TOP|NOP]__()
//
// RAM:
// PUSH__RAM(some_addr,some_data)
// POP__RAM(some_addr)
// TOP__RAM(some_addr)
// NOP__RAM
//
// STACK:
// PUSH__STACK(some_data)
// POP__STACK
// TOP__STACK
// NOP__STACK
//
// QUEUE:
// PUSH__STACK(some_data)
// POP__STACK
// TOP__STACK
// NOP__STACK
//
// Remark: All NOP operations prevent only write accesses, i.e. memory modifications
//
// ********
// ATTENTION! Invoking a memory operation for set_output will cause another memory access
// ATTENTION! Use the output signal of the memory instead!
// ********
//
// Example: Assuming a STACK named MY and a RAM named MY.
// S0, some_condition & (POP_MY_RAM(some_addr)==some_input_data), S1, some_output=MY_RAM_rd_data, PUSH_MY_RAM(some_addr,some_data)/PUSH_MY_STACK(some_data)
//
ID, IDLE, ID, mesi<=ZERO/index<=addr[7:2], NOP_TAG_RAM/NOP_MESI_RAM
ID, READ & TAG_MATCH & ~MESI_IS_ZERO, RD, mesi<=EXCLUSIVE/index<=addr[7:2], ?SET_EXCLUSIVE/NOP_TAG_RAM
ID, READ & ( ~TAG_MATCH | MESI_IS_ZERO ), RD, mesi<=EXCLUSIVE/index<=addr[7:2], ?SET_EXCLUSIVE/?SET_TAG
ID, WRITE & TAG_MATCH, WR, mesi<=MODIFIED/index<=addr[7:2], ?SET_MODIFIED/NOP_TAG_RAM
ID, rWRITE & TAG_MATCH, rWR, mesi<=INVALID/index<=addr[7:2], ?SET_INVALID/NOP_TAG_RAM
ID, rREAD & TAG_MATCH, rRD, mesi<=SHARED/index<=addr[7:2], ?SET_SHARED/NOP_TAG_RAM
ID, rREAD & ~TAG_MATCH, ID, mesi<=ZERO/index<=addr[7:2], NOP_MESI_RAM/NOP_TAG_RAM
RD, IDLE, ID, mesi<=ZERO, NOP_TAG_RAM/NOP_MESI_RAM
RD, READ & TAG_MATCH & ~MESI_IS_ZERO, RD, mesi<=EXCLUSIVE/index<=addr[7:2], ?SET_EXCLUSIVE/NOP_TAG_RAM
RD, READ & (~TAG_MATCH | MESI_IS_ZERO), RD, mesi<=EXCLUSIVE/index<=addr[7:2], ?SET_EXCLUSIVE/?SET_TAG
WR, IDLE, ID, mesi<=ZERO/index<=addr[7:2], NOP_TAG_RAM/NOP_MESI_RAM
WR, WRITE & TAG_MATCH, WR, mesi<=MODIFIED/index<=addr[7:2], ?SET_MODIFIED/NOP_TAG_RAM
WR, WRITE & ~TAG_MATCH, ID, mesi<=ZERO/index<=addr[7:2], NOP_TAG_RAM/NOP_MESI_RAM
rRD, IDLE, ID, mesi<=ZERO/index<=addr[7:2], NOP_TAG_RAM/NOP_MESI_RAM
rRD, rREAD & TAG_MATCH & ~MESI_IS_ZERO, rRD, mesi<=SHARED/index<=addr[7:2], ?SET_SHARED/NOP_TAG_RAM
rRD, rREAD & ( ~TAG_MATCH | ( TAG_MATCH & MESI_IS_ZERO ) ), ID, mesi<=ZERO/index<=addr[7:2], NOP_TAG_RAM/NOP_MESI_RAM
rWR, IDLE, ID, mesi<=ZERO/index<=addr[7:2], NOP_TAG_RAM/NOP_MESI_RAM
rWR, rWRITE & TAG_MATCH & ~MESI_IS_ZERO, rWR, mesi<=INVALID/index<=addr[7:2], ?SET_INVALID/NOP_TAG_RAM
rWR, rWRITE & ~TAG_MATCH | (TAG_MATCH & MESI_IS_ZERO), rWR, mesi<=ZERO/index<=addr[7:2], NOP_MESI_RAM/NOP_TAG_RAM
ZERO = 4'b0000
MODIFIED = 4'b1000
EXCLUSIVE = 4'b0100
SHARED = 4'b0010
INVALID = 4'b0001
IDLE = ~res_n | (~rd & ~wr)
READ = res_n & cp & rd
rREAD = res_n & ~cp & rd
WRITE = res_n & cp & wr
rWRITE = res_n & ~cp & wr
TAG_MATCH = POP_TAG_RAM(addr[7:2])==addr[31:8]
MESI_IS_ZERO = POP_MESI_RAM(addr[7:2])==ZERO
IS_MODIFIED = POP_MESI_RAM(addr[7:2])==MODIFIED
IS_EXCLUSIVE = POP_MESI_RAM(addr[7:2])==EXCLUSIVE
IS_SHARED = POP_MESI_RAM(addr[7:2])==SHARED
IS_INVALID = POP_MESI_RAM(addr[7:2])==INVALID
?SET_MODIFIED = PUSH_MESI_RAM(addr[7:2],MODIFIED)
?SET_EXCLUSIVE = PUSH_MESI_RAM(addr[7:2],EXCLUSIVE)
?SET_SHARED = PUSH_MESI_RAM(addr[7:2],SHARED)
?SET_INVALID = PUSH_MESI_RAM(addr[7:2],INVALID)
?SET_TAG = PUSH_TAG_RAM(addr[7:2],addr[31:8])
//
// is terminated by
// defines the initial code sequence for the Verilog simulator
// it is recommended to assign reg instances
STATE <= ID;
//
//
// is terminated by
// defines an instance of memory of type ram, stack or queue
// NAME is the instance name
// connecting signals are prefixed NAME_type_signalname,
// e.g. TAG_RAM_wr, where TAG is the name, ram is the type and rd is the signal name
// NAME, type, width, entries, list of inputs separated by whitespace, list of outputs separated by whitespace
//
// Example:
// TAG, ram, 24, 64, clk res wr wr_addr[6-1:0] wr_data[24-1:0] rd rd_addr[6-1:0] STATUS, rd_data[24-1:0]
// ATTENTION! STATUS is mandatory to meet Verilog function return value requirements. Use TAG_RAM_status
// for example but just status for all memories should work as well
//
TAG, ram, 24, 64, TAG_RAM_clk TAG_RAM_res TAG_RAM_wr TAG_RAM_wr_addr[5:0] TAG_RAM_wr_data[23:0] TAG_RAM_rd TAG_RAM_rd_addr[5:0] TAG_RAM_status, TAG_RAM_rd_data[23:0]
MESI, ram, 4, 64, MESI_RAM_clk MESI_RAM_res MESI_RAM_wr MESI_RAM_wr_addr[5:0] MESI_RAM_wr_data MESI_RAM_rd MESI_RAM_rd_addr[5:0] MESI_RAM_status, MESI_RAM_rd_data[3:0]
//
// is terminated by
// verigen creates a testbench _tb.v
// ports of .v are prefixed with tb_
// lines are dropped in the _tb.v unmodified
// __Test__
// __Reset__
tb_res_n = 1'b0; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #30;
tb_res_n = 1'b1; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #20;
// __Read__
tb_res_n = 1'b1; tb_addr = 32'hDEAD_BEEF; tb_cp = 1; tb_rd = 1; tb_wr = 0; #10;
// __Idle50__
tb_res_n = 1'b1; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #50;
// __ReadRemote__
tb_res_n = 1'b1; tb_addr = 32'hDEAD_BEEF; tb_cp = 0; tb_rd = 1; tb_wr = 0; #10;
// __Idle50__
tb_res_n = 1'b1; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #50;
// __WriteRemote__
tb_res_n = 1'b1; tb_addr = 32'hDEAD_BEEF; tb_cp = 0; tb_rd = 1; tb_wr = 0; #10;
// __Idle100__
tb_res_n = 1'b1; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #100;
// __Read__
tb_res_n = 1'b1; tb_addr = 32'h0000_BEEF; tb_cp = 0; tb_rd = 1; tb_wr = 0; #10;
// __Idle50__
tb_res_n = 1'b1; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #50;
// __ReadRemote__
tb_res_n = 1'b1; tb_addr = 32'h0000_BEEF; tb_cp = 1; tb_rd = 1; tb_wr = 0; #10;
// __Idle50__
tb_res_n = 1'b1; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #50;
// __Write__
tb_res_n = 1'b1; tb_addr = 32'h0000_BEEF; tb_cp = 0; tb_rd = 0; tb_wr = 1; #10;
// __Idle100__
tb_res_n = 1'b1; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #100;
// __End of Test__
//
// is ended by
// can be set true of false
// if true, verigen inserts NOP memory operations in case of no memory action
// set to false by default
// use false setting if FSMs are designed
// try true setting if recurrent memory operations on state changes occur
// true setting recommended in case of Extended PDA
//
// **********************************************************
// TODO, this function is in ERROR and needs to be fixed!
// DO NOT USE IT FOR THE MOMENT!!!
// Just keep it set to 'false' and you're doing fine!
// **********************************************************
//
false
// end is mandatory to trigger Verilog compilation
end
VERIGEN_FREE/mesi/irun.sh 0000755 0001750 0001750 00000000440 13377751300 015107 0 ustar mfertig mfertig #/bin/bash
echo "Invoke irun ..."
irun \
-access +rw \
-input @'database -open waves -into waves.shm -default' \
-input @'probe -create [scope -tops] -depth all -tasks -functions -all -memories -database waves' \
-status \
MESI_tb.v \
-V200X \
-smartorder \
-top MESI_tb \
-gui
VERIGEN_FREE/mesi/MESI_tb.v 0000664 0001750 0001750 00000004031 13377757552 015225 0 ustar mfertig mfertig // testbench generated by verigen.pl on Thu Nov 29 13:44:28 2018
// input file: mesi.cfg
`include "./MESI.v"
module MESI_tb();
reg tb_clk;
reg tb_res_n;
reg [31:0] tb_addr;
reg tb_cp;
reg tb_rd;
reg tb_wr;
wire [3:0] tb_mesi;
wire [5:0] tb_index;
MESI dut(
.clk(tb_clk),
.res_n(tb_res_n),
.addr(tb_addr),
.cp(tb_cp),
.rd(tb_rd),
.wr(tb_wr),
.mesi(tb_mesi),
.index(tb_index)
);
always begin
#5 tb_clk = ~tb_clk;
end
initial begin
$dumpfile ("MESI_tb.vcd");
$dumpvars;
end
initial begin
tb_clk <= 1'b1;
// __Test__
// __Test__
// __Reset__
tb_res_n = 1'b0; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #30;
tb_res_n = 1'b1; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #20;
// __Read__
tb_res_n = 1'b1; tb_addr = 32'hDEAD_BEEF; tb_cp = 1; tb_rd = 1; tb_wr = 0; #10;
// __Idle50__
tb_res_n = 1'b1; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #50;
// __ReadRemote__
tb_res_n = 1'b1; tb_addr = 32'hDEAD_BEEF; tb_cp = 0; tb_rd = 1; tb_wr = 0; #10;
// __Idle50__
tb_res_n = 1'b1; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #50;
// __WriteRemote__
tb_res_n = 1'b1; tb_addr = 32'hDEAD_BEEF; tb_cp = 0; tb_rd = 1; tb_wr = 0; #10;
// __Idle100__
tb_res_n = 1'b1; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #100;
// __Read__
tb_res_n = 1'b1; tb_addr = 32'h0000_BEEF; tb_cp = 0; tb_rd = 1; tb_wr = 0; #10;
// __Idle50__
tb_res_n = 1'b1; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #50;
// __ReadRemote__
tb_res_n = 1'b1; tb_addr = 32'h0000_BEEF; tb_cp = 1; tb_rd = 1; tb_wr = 0; #10;
// __Idle50__
tb_res_n = 1'b1; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #50;
// __Write__
tb_res_n = 1'b1; tb_addr = 32'h0000_BEEF; tb_cp = 0; tb_rd = 0; tb_wr = 1; #10;
// __Idle100__
tb_res_n = 1'b1; tb_addr = 32'h0000_0000; tb_cp = 0; tb_rd = 0; tb_wr = 0; #100;
// __End of Test__
// __End of Test__
end
endmodule // MESI_tb();
VERIGEN_FREE/mesi/irun.sh~ 0000755 0001750 0001750 00000000456 13377751240 015317 0 ustar mfertig mfertig #/bin/bash
echo "Invoke irun ..."
irun \
-access +rw \
-input @'database -open waves -into waves.shm -default' \
-input @'probe -create [scope -tops] -depth all -tasks -functions -all -memories -database waves' \
-status \
SIMPLE_MEM2_tb.v \
-V200X \
-smartorder \
-top SIMPLE_MEM2_tb \
-gui
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